Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond
To date, transistor scaling has continued in accordance with Moore’s Law down to 32 nm. Engineering challenges, however, are forcing chipmakers to compromise performance and power efficiency in order to reach smaller nodes – unless they switch to new technologies that help better solve these challenges. Today, the semiconductor industry is starting to deploy such new technologies, largely relying on “fully-depleted” transistors for continued scaling and performance gains.
Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond - [Link]
